1. Field of the Invention
The present invention generally relates to a liquid crystal display and display panel thereof, and more particularly, to a liquid crystal display and display panel thereof which may selectively receive a common voltage by using pixel row units.
2. Description of Related Art
Nowadays, a liquid crystal display (LCD) is widely used, and has replaced cathode ray tube (CRT) display. Therefore, it has become one of the mainstream display for the next generation displays. With the development of the semiconductor technology, several large size liquid crystal displays have been developed, but which also poses another technical challenge, namely flicker noise tends to be more serious in larger size display panel.
There are two kinds of structures for the pixel unites in a conventional display panel, one is as shown in the schematic view for illustrating the structure, of a pixel unit 100 in FIG. 1, and the other is as shown in the schematic view for illustrating the structure of a pixel unit 200 in FIG. 2. Referring to FIG. 1 and FIG. 2, the pixel units 100 and 200 respectively comprise a transistor 101, a liquid crystal capacitance CLC, a storage capacitance CS, and a parasitic capacitance Cgd. And the greatest difference is that the design of the storage capacitance CS is on a common voltage (Vcom) (CS on common) in the pixel unit 100, and the design of the storage capacitance CS is on a scan line Gm-1(CS on gate) in the pixel unit 200.
Regardless of the structure for pixel unit used, when a gate signal SG outputted from a gate driver (not shown) is rapidly reduced from a high potential VH to a low potential VL to result in turning off the transistor 101, and coupling effect caused by the parasitic capacitance Cgd will result in decrease in the drain voltage VD of the transistor 101 by a potential difference ΔVFT, which may be expressed by the equation (1):
                              Δ          ⁢                                          ⁢                      V            FT                          =                                            C              gd                                                      C                gd                            +                              C                s                            +                              C                LC                                              ⁢          Δ          ⁢                                          ⁢                      V            GP                                              (        1        )            wherein ΔVGP=VH−VL, and the potential difference ΔVFT is referred to as a feed-through voltage. We can know from the equation (1) that because the feed-through voltages ΔVFT of the pixel units in conventional display panels are not completely same, there will result in flicker noises of display panels, so as to increase the flicker noise of the liquid crystal display.
In order to decrease the flicker noise generated by feed-through effect mentioned above, known methods have developed various methods for resolving the problem, comprising:
1. modifying the common voltage provided to the display panel according to the feed-through voltage ΔVFT; and
2. using the driving method of a third or fourth order gate signal.
FIG. 3 is a waveform diagram for illustrating the related methods mentioned above. It is suitable for the pixel unit 100 disclosed above. Referring to FIG. 1 and FIG. 3, when the gate signal SG is a high potential VH, the transistor 101 is turned on. At the same time, the source voltage VS transmitted over the data line SL will be stored on the liquid crystal capacitance VLC, such that the potential of the drain voltage VD will be changed to as the potential of the source voltage VS. However, when the gate signal SG is rapidly reduced from the high potential VH to the low potential VL, the potential of drain voltage VD will be reduced by a feed-through voltage ΔVFT. In order to eliminate the flicker noise caused by the feed-through voltage ΔVFT, the related method 1 modifies the common voltage Vcom of the display panel to the optimum common voltage V′com.
However, it must perform a complicated hand measurement to determine the optimum common voltage V′com provided to the display panel at the beginning of modifying the common voltage Vcom by the related method 1. Furthermore, the properties of each display panel are not completely the same, so the optimum common voltage V′com determined above will not meet completely each display panel.
FIG. 4 is a waveform diagram for illustrating the related method mentioned above. It is suitable for the pixel unit 200 disclosed above. Referring to FIG. 2 and FIG. 4, when the potential of the drain voltage VD is reduced by a quality of a feed-through voltage ΔVFT, the potential of the drain voltage VD will be stepped charged to the potential of the source voltage VS by the compensating voltage VP provided by the gate signals SGm-1 and SGm during the low potential period in the related method 2.
However, the compensating voltage VP provided by the related method 2 will be calculated out according to a theoretical equation, but the gate signal SG is generated by the gate driver in the liquid crystal display in the actual application. Thus, during the period of increasing the accuracy on the compensating voltage VP, the complexity of the design on the gate driver is also increased. Therefore, when the related method 2 eliminates the flicker noise of the liquid crystal display, the complexity of the design on the gate driver is also increased. As the result, the liquid crystal display will have more layout area and more waste of the power.